MTS Silicon Design Engineer

🎯 Role Definition

As a Member of Technical Staff (MTS) in Silicon Design, you are a critical individual contributor and a technical authority at the heart of our semiconductor development efforts. This role is not just about writing code; it's about owning a significant piece of the chip, from initial architectural concept through to final tape-out and silicon bring-up. The MTS Silicon Design Engineer drives the micro-architectural definition and implementation of complex, high-performance, and power-efficient digital logic for our next-generation SoCs and ASICs. You will be the go-to expert for your design block, collaborating deeply with cross-functional teams including architecture, verification, physical design, and software to deliver state-of-the-art silicon products that push the boundaries of technology.

📈 Career Progression

Typical Career Path

Entry Point From:

Senior Silicon Design Engineer
Senior ASIC Design Engineer
Digital Design Engineer with significant project ownership

Advancement To:

Senior MTS Silicon Design Engineer
Principal Silicon Design Engineer
Technical Lead or Chip Lead
Design Engineering Manager

Lateral Moves:

Design Verification Engineer (Principal Level)
Silicon Architect
Physical Design Engineer (Principal Level)

Core Responsibilities

Primary Functions

Take ownership of the micro-architecture definition for complex digital blocks, translating high-level architectural specifications into detailed, implementable designs.
Develop, and deliver high-quality, synthesizable RTL code in SystemVerilog or Verilog, ensuring it meets stringent performance, power, and area (PPA) goals.
Perform and oversee all front-end design activities, which includes block-level RTL creation, IP integration, and top-level SoC integration.
Run synthesis and analyze results to drive PPA optimizations, iterating with the physical design team to achieve challenging frequency and power targets.
Conduct rigorous static timing analysis (STA) to identify and resolve timing violations, working hand-in-hand with the implementation team for timing closure.
Champion design quality by performing thorough linting, Clock Domain Crossing (CDC), and Reset Domain Crossing (RDC) analysis and ensuring all identified issues are resolved.
Collaborate proactively with the Design Verification team to craft comprehensive verification test plans and actively participate in debugging complex simulation failures.
Develop and refine timing constraints (SDC) for synthesis and STA, ensuring they are accurate and complete for successful physical implementation.
Drive power-aware design methodologies, from architectural decisions to implementing techniques like clock gating, power gating, and multi-voltage domains using UPF.
Contribute to post-silicon validation efforts, including developing test plans, debugging hardware in the lab, and correlating silicon behavior with simulation models.
Create and maintain meticulous design documentation, including micro-architecture specifications, block diagrams, and register maps.
Evaluate, select, and integrate third-party IP, ensuring it meets all functional, performance, and quality requirements for the project.
Guide and implement the Design for Test (DFT) strategy for your blocks, collaborating with test engineers to maximize test coverage and manufacturability.
Act as a technical mentor for junior engineers, sharing your expertise, conducting knowledge-sharing sessions, and leading by example in technical excellence.
Interface directly with software, firmware, and systems teams to ensure seamless hardware-software co-design and successful system-level integration.
Analyze performance bottlenecks within the design using performance models or simulation data, proposing and implementing enhancements to boost efficiency.
Participate in and often lead formal design reviews, presenting your work to peers and leadership and providing insightful feedback on other designs.
Drive the continuous improvement of our design methodologies and automation flows by developing and maintaining scripts in languages like Python, Perl, or Tcl.
Engage with the architecture team to provide critical feedback on next-generation product specifications, ensuring they are well-defined and feasible to implement.
Support FPGA prototyping and emulation efforts by adapting RTL and working with the emulation team to enable early software development and system validation.

Secondary Functions

Support ad-hoc silicon validation, characterization, and customer-reported debug efforts.
Contribute to the evolution of the organization's design methodology, tools, and best practices.
Collaborate with business units and marketing to translate future product needs into technical requirements for the hardware roadmap.
Participate in sprint planning and agile-style project management ceremonies to ensure predictable execution and delivery.

Required Skills & Competencies

Hard Skills (Technical)

Deep expertise in digital logic design and RTL development using SystemVerilog and/or Verilog.
Strong, hands-on experience with the complete ASIC/SoC front-end design flow, from micro-architecture to synthesis and timing closure.
Proficiency with a suite of industry-standard EDA tools for simulation (e.g., Synopsys VCS, Cadence Xcelium), synthesis (e.g., Synopsys Design Compiler, Cadence Genus), and static timing analysis (e.g., Synopsys PrimeTime, Cadence Tempus).
A solid foundation in computer architecture principles, including knowledge of CPUs, GPUs, cache coherency, memory controllers, and on-chip interconnects.
Advanced scripting skills for automation and data analysis using languages such as Python, Perl, or Tcl.
In-depth understanding and practical application of low-power design techniques and methodologies (UPF, clock gating, power gating).
Proven experience with static analysis tools and methodologies for lint, Clock Domain Crossing (CDC), and formal verification (e.g., SpyGlass, JasperGold).
Familiarity with Design for Test (DFT) and Design for Debug (DFD) concepts and implementation.
Experience with post-silicon bring-up, debug, and the use of lab equipment like logic analyzers and oscilloscopes.
Knowledge of version control systems like Git or Perforce.

Soft Skills

Exceptional analytical and problem-solving skills, with a knack for debugging complex, system-level issues.
A highly collaborative mindset with excellent interpersonal and communication skills to work effectively across diverse engineering disciplines.
Strong sense of ownership and personal accountability for deliverables and project success.
Ability to work independently with minimal supervision, demonstrating a proactive and self-motivated approach.
Innate curiosity and a passion for continuous learning to stay at the forefront of semiconductor technology.

Education & Experience

Educational Background

Minimum Education:

Bachelor of Science (B.S.) in a relevant technical field.

Preferred Education:

Master of Science (M.S.) or Doctorate (Ph.D.) in a relevant technical field.

Relevant Fields of Study:

Electrical Engineering (EE)
Computer Engineering (CE)
Computer Science (CS)

Experience Requirements

Typical Experience Range: 5-12 years of relevant experience in ASIC, SoC, or IP design.

Preferred: 8+ years of experience with a proven track record of taking multiple complex design blocks or chips through the entire development lifecycle to tape-out.